Nora
AI agent & framework for physical design automation. Analyzes PrimeTime reports to suggest optimal fixes (buffer sizing, net splitting) and auto-generates Fusion Compiler placement commands with EMIR compliance.
ML for chip design @ Tenstorrent · Computer Engineering @ McMaster & NTU
I'm Sameer, a computer engineering student at McMaster (and an exchange term at NTU Singapore) working on machine learning for chip design. Currently a physical design intern at Tenstorrent.
B.Eng Computer Engineering (GPA 4.0/4.0) · Hamilton, Ontario
Coursework: Microelectronics, VLSI, Digital Systems Design, Control Systems, DSP, DSA I & II
Exchange Term, School of EEE (GPA 5.0/5.0) · Singapore
Coursework: GPU Programming, Computer Architecture, Embedded Systems
Tenstorrent · Santa Clara, CA
AMD · Markham, Ontario
AI agent & framework for physical design automation. Analyzes PrimeTime reports to suggest optimal fixes (buffer sizing, net splitting) and auto-generates Fusion Compiler placement commands with EMIR compliance.
ML-guided buffer insertion for timing ECOs. GAT/GBR model that recovers slack along timing paths, ranking the best fixes per violating path and generating ECO TCL for signoff.
Macro floorplanning algorithm. Hybrid CPU/GPU placer chaining DREAMPlace seeding, a GNN candidate ranker, and congestion-gradient shifting to reach 1.1252 avg score on IBM ICCAD04 benchmarks.
Best reached by email at sameersul03@gmail.com or by phone at +1 (437) 993-2171.