I'm Sameer — a computer engineering student at McMaster (and an exchange term at NTU Singapore) working on machine learning for chip design. I build LLM agents, graph neural networks, and lightweight CAD tools that compress the slow, manual parts of physical design and verification. Currently an ML intern at Tenstorrent.
Exchange Term, School of EEE · Singapore
Coursework: GPU Programming, Computer Architecture, Embedded Systems, AI & Data Mining
B.Eng Computer Engineering (GPA 4.0 / 4.0) · Hamilton, ON
Coursework: Data Structures & Algorithms, Microelectronics, Machine Learning, Digital Design, Logic Design, DSP, Control Systems, ARM Microprocessors
Tenstorrent · Santa Clara, CA · May 2026 – Present
LLM agent for Synopsys Formality FEV fix proposals, a D2D tile diagram generator from SystemVerilog filelists, and a GAT-based buffer-insertion ECO ranker paired with a DEF chip viewer 170× faster than Innovus/OpenSTA crossprobe.
AMD · Markham, ON · May 2025 – Jan 2026
LangChain agent parsing PrimeTime violations (−40% resolution time), GNN for slack regression (−32% PBA path set), a multi-corner timing predictor, and a conditional GAN forecasting routing congestion at 87.3% accuracy.
McMaster University (HADI Lab) · Hamilton, ON · Sep – Dec 2025
Calibration-free BMI decoder using Banditron RL with adaptive channel masking — 96% accuracy at 3 MACs/inference, sub-mW power.
Hierarchy-driven macro placer using grouped DREAMPlace initialization, congestion-aware relocation, and cluster-consecutive legalization — 1.1999 avg score, zero-overlap placements across IBM ICCAD04.
GAT-based Graph Neural Network on timing-path subgraphs to score buffer-insertion candidates per violating path, ranking ECOs by predicted slack impact; exported to ONNX for low-latency signoff inference.
Best reached by email at sulems6@mcmaster.ca, or on LinkedIn and GitHub below.